88 france English-speaking jobs in Cannes - Crasse

The position may require travel in France and abroad.

This position is permanent, and the preferred location is Belgrade, Serbia, Germany, France, UK, Sweden

issues with creative solutions.Must be willing to travel as required.More information about NXP in France

and conversation intelligence toolsWhy to join usWe are based in Sophia-Antipolis, in the South of France

The Stylist provides exceptional customer service and builds lasting relationships with clients to meet sales goals. They possess expert knowledge of the brand, aesthetic, and pieces, and actively learn and speak to current fashion trends.

supporting the complete application lifecycle for all SAP solutions.This apprenticeship is based in SAP Labs France

Applies machine learning to ultrasound transducer design, development, and manufacturing. Defines project requirements, collaborates with stakeholders, and delegates tasks. Requires experience in acoustics, ultrasound, machine learning, and cloud environments.

System, Network Security Administration apprenticeship supporting IT infrastructure including workstations, servers, networks, and internal services. Responsibilities include website administration, software testing, and customer support. Fluent English required.

Senior Site Reliability Engineer will manage global AWS services, participate in on-call rotations, and build CI/CD solutions. Requires experience with AWS, Kubernetes, Infrastructure-as-Code, Unix/Linux, and CI/CD tools.

Project Sales Engineer supporting Business Development Managers in shipbuilding. Prepare project quotations, process customer orders, and provide technical advice. Requires experience with NAV/COM equipment, excellent English communication skills, and a vocational degree or equivalent.

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.

Define and optimize cache coherency solutions for Arteris' IP portfolio. Develop cache-coherent interconnect IP and ensure seamless integration with NoC interconnects and system IP. Collaborate with hardware designers, verification engineers, and software developers.

Manages the Product Information Management (PIM) platform (Salsify), ensuring data quality, governance, rollout, and adoption. Aligns cross-functional teams to optimize product data management and evolve the data model. Leads change management initiatives, promotes data quality, and provides technical support.

The Director of Sales – MICE will define and execute the international MICE strategy, focusing on European & Northern American markets for luxury corporate & incentive segments. The role involves leading a team of 4, growing an international portfolio, and securing key accounts.

Post-Doctoral Research Visit in Software Language Engineering. The researcher will apply their skills in defining an innovative modeling and development environment for Software Defined Vehicles. PhD degree in computer science, software engineering, embedded systems, or a related field required. Proficiency in one of the following research fields: Language Engineering, Modeling and Simulation, Formal Analysis, Contract Based Design, Innovative Development Methods and Tools.

Java Developer will design, develop, and test technical solutions for a client specializing in personal and property security. The role involves working on both an existing Oracle/PL/SQL system and a new Java 17, Spring, Kafka, and Jenkins system with a distributed architecture.

Develop and execute test plans and verification methodologies for SoC-level designs. Complete functional verification to required quality standards and schedules. Collaborate with project leads and management on planning, scheduling, and quality checkpoints. Ensure progress and quality of SoC verification activities. Work closely with teams across architecture, design, implementation, modeling, performance analysis, silicon validation, FPGA, and board development. Mentor and guide junior verification engineers.

Digital Design Engineer to develop Bluetooth IP solutions. Define micro-architecture, implement designs, and support validation and customer support. Requires 3+ years of digital design experience, Verilog/SystemVerilog proficiency, and FPGA implementation skills.

Senior Layout Designer will design analog/mixed-signal layouts for PMICs in high-end electronic devices. Responsibilities include collaborating with design engineers, improving layout methodologies, and troubleshooting issues. Requires a Bachelor's degree in Electronics Engineering and at least 6 years of experience. Strong Cadence Virtuoso Suite and Calibre verification tools knowledge is essential.

Support the coordination and operational execution of 3GPP meetings hosted by ETSI. Assist with planning, logistics, administration, onsite support, and vendor management. Collaborate with internal and external stakeholders to ensure successful meeting delivery.