40 English-speaking jobs in Cannes - Crasse

IT Business Analyst assesses and analyzes business requirements. Responsibilities include functional design, writing specifications, validating product functionality, and managing stakeholder relations across the product lifecycle. A Master's degree in Computer Science is required.

Design and implement a next-generation agentic AI system integrating Knowledge Graphs (KG), Large Language Models (LLMs), and autonomous agents to power SAP service and support capabilities. Construct a rich, multi-source knowledge graph by ingesting and connecting heterogeneous SAP data. Develop LLM-powered agents capable of reasoning over interconnected knowledge and translating complex natural language queries into SPARQL.

Service Reliability Engineer (SRE) or DevOps will accelerate application delivery by developing automation for managed services. Responsibilities include building tools and processes, scripting automation, and collaborating with various teams on projects.

Network Security QA Engineer role involves post-sales testing to replicate customer environments. Requires strong network security experience, knowledge of TCP/IP, and proficiency with tools like Spirent/Ixia.

Senior Principal Test Engineer develops industrial test solutions (hardware and software) for mass production of Analog/RF&mmWave products. This role involves test strategy, ATE development, and supporting design from specification through release.

Consulting Systems Engineer supporting FortiADC, FortiDDoS, and FortiCASB. Provide second-level pre-sales support, lead technical discussions, and build sales materials for the INTL region. Requires 8 years of technical pre-sales experience.

Consulting Systems Engineer relays Public Cloud expertise to sales teams, customers, and partners. Responsibilities include conducting PoVs, researching integrations, and supporting technical discussions for Fortinet's cybersecurity offerings.

Senior Full-Stack Developer needed for Fortinet EMEA Labs. Design and develop complex application modules for network security infrastructure. Requires 5+ years experience, proficiency in React, Python, node.js, and RESTful APIs.

Senior CAD flow engineer will define, deploy, and improve ASIC development methodology and design flow. Responsibilities include leading tool evaluation and optimization, providing technical support to development teams, and acting as a technical interface with vendors.

Senior IP subsystem SoC architect will define, drive, and evolve IP, subsystem, and SoC architectures. Responsibilities include breaking down architectures into functional sub-blocks, writing specifications, and supporting RTL, physical design, verification, and software prototyping teams.

Senior Emulation Engineer/Team Lead to drive emulation strategy and workflows for complex CPUs. Lead the team, define project tasks, and optimize platform deliveries using ASIC and emulation platform expertise.

Define, document, and drive system architecture for cutting-edge HPC systems. Lead architectural engagements with partners and customers to design optimized HPC nodes. Develop integration, performance measurement, and optimization tools. Contribute to collaborative projects, technical deliverables, and partner workshops. Support customers in migrating applications toward new system architectures.

System Software Validation Engineer to ensure quality and reliability of software solutions. Design and execute test strategies, develop test cases, and verify firmware/software stacks. Requires 7+ years in software testing and strong technical knowledge.

Emulation Engineer role at SiPearl involves contributing to emulation setup, RTL adaptation, and pre-silicon verification. Key tasks include developing workflows, maintaining models, and supporting platform users. Requires 6+ years in digital ASIC and 4+ years on emulation platforms.

Experienced Project Engineer needed to manage complex Engineer-to-order projects in a marine environment. Own technical scope, lead discussions with shipyards and customers, and ensure successful project execution from handover to delivery.

Principal Design Verification Engineer to design and deliver interconnect & memory hierarchy solutions for sophisticated SoCs. Responsibilities include UVM test bench development, RTL verification, and improving verification processes using scripting.

This hybrid role requires hands-on technical ownership of building systems at the Sophia Antipolis site while standardizing maintenance and technical practices across EMEA. Responsibilities include site operations, vendor management, and process improvement.

Senior Satellite Systems Engineer provides resident systems engineering support across satellite procurement phases, overseeing spacecraft Design, Assembly, Integration, and Launch. Responsibilities include reviewing test data and mitigating technical risks.

Senior Verification Engineer to verify RTL for ARM SoC features. Requires 5+ years in IP/SOC verification, proficiency in SystemVerilog/UVM, and experience with ARM designs.

Lead SoC Interconnect Technology Team to drive architecture and design of coherent/non-coherent interconnect solutions. Requires 15+ years in SoC architecture with expertise in scalable fabrics, performance, and power optimization.