109 English-speaking jobs in Cannes - Crasse

A postdoctoral position is available to evaluate the usability of "notice and action" reporting mechanisms on online platforms within the context of the EU Digital Services Act (DSA). The successful candidate will apply usability evaluation methods to assess the effectiveness and user-friendliness of these mechanisms.

This PhD position at GRAPHDECO explores novel view synthesis using radiance fields in computer graphics. The research focuses on creating, editing, and rendering realistic 3D environments by bridging traditional computer graphics and scene capture approaches.

This 2-year postdoc position aims to develop a domain-agnostic algorithm for segmenting brain MRI scans across the human lifespan. The successful candidate will work with two leading research groups in medical image analysis, Inria and University College London. The project will extend domain randomisation to capture the unique characteristics of foetal and infant brains, integrating early-life and adult data into a single training framework.

Graduate engineer to join CPU verification team, developing and deploying a Random Instruction Sequences (RISC) tool. Responsibilities include gathering requirements, architecting solutions, and implementing, maintaining, and supporting the tool.

SiPearl seeks a Technical Project Manager with expertise in IP governance and engineering project enablement. This role establishes a secure, compliant, and efficient engineering environment. Responsibilities include partnering with engineering teams on project startup requirements, collaborating with IT, HR, and engineering for smooth execution, and managing scope changes. The ideal candidate has extensive experience in technical project management, third-party IP management, and engineering tool ecosystems.

Investigate performance issues and suggest product improvements for Arm's Cloud Server System-on-a-Chip. Analyze the performance of Arm CPUs and Interconnect IPs.

Senior IP Qualification Engineer will verify Third-Party IPs (standard-cells, memories, interfaces) before embedding in Arm SoCs. Responsibilities include ensuring RTL design and EDA models align with Arm SoC design flow, verifying methodology, and analyzing interface IP behavior. Requires 5+ years experience in RTL, low-power verification, scripting, and System Verilog.

Graduate engineer to join CPU verification team. Responsibilities include gathering requirements, understanding CPU micro-architecture, and developing solutions to improve test stimuli generation. Requires proficiency in programming and scripting languages, understanding of assembly language, and strong interpersonal skills.

Manages and develops ETSI's website, ensuring a consistent look and feel across all pages. Develops and maintains web editing guidelines, manages the editorial calendar, and reviews content. Creates digital assets (text, images, videos) aligned with the marketing communication plan. Tracks website performance and proposes improvements. Promotes ETSI activities online and manages social media support.

This Systems Validation Engineer role focuses on verifying NoC solutions and CPU to DDR performance targets within a full system. Responsibilities include defining and implementing validation plans, running test cases, and participating in performance analysis and automation.

Momji seeks a part-time English nanny for 6 hours per week in AURIBEAU SUR SIAGNE, starting August 24, 2026. Responsibilities include after-school and daycare pick-ups, homework help, snack time, assisting with hygiene, and park visits. Previous experience with children is required. EU citizenship or a work visa for France is necessary.

CPU Verification Intern will contribute to verifying Arm Cortex IPs using various methodologies, tools, and programming languages. Interns will work on real projects, enhancing unit-level verification environments and improving defect detection on Silicon.

Consulting Systems Engineer provides Public Cloud expertise to Sales, Sales Engineers, and Subject Matter Experts. Conducts PoVs, researches integrations with Fortinet's cybersecurity offerings, and supports key projects. Requires pre-sales experience, cloud platform knowledge (AWS, Azure, GCP), and strong presentation skills.

System Administrator Engineer to manage and optimize a technical infrastructure for Fortinet product validation. Responsibilities include Linux server and virtual machine administration, Docker container management, traffic generator administration, monitoring and alerting solutions management, application support, and ITIL process adherence.

Fortinet seeks Consulting Systems Engineers with deep networking and security knowledge to join the FortiGate/SASE Enterprise team. Responsibilities include providing design assistance, architectural advice, and product insight to sales staff. Candidates will conduct lab testing, deliver results through written documents and meetings, and provide technical assistance to sales teams. Strong networking skills, including IPv4/IPv6, routing protocols, VPNs, and security expertise are required. Excellent communication and presentation skills are also essential.

IT Support Technician provides first and second-level support to end users, troubleshooting hardware and software issues. Responsibilities include assembly, installation, and monitoring of IT equipment, on-site and remote intervention for technical issues, and ensuring network and data security.

Intern will investigate architecture enhancements for the Scalable Matrix Extension (SME), supporting AI, Machine Learning, Computer Vision, telecommunication, and HPC applications. Responsibilities include analyzing applications and prototyping innovative instructions.

Senior Full-Stack Developer will design, develop, and deliver application modules for network security infrastructure. Requires 5+ years of experience in full-stack development, proficiency in JavaScript, HTML5, CSS3, Python, and Perl, and experience with RESTful APIs and web services.

Embedded Software Engineers develop next generation Wi-Fi technologies using low-level C for wireless communications and subsystems.

Designs and implements system level platforms for RTL simulation and FPGA emulation using Snapdragon IPs. Integrates CPUs, SMMU, interconnects, and memory controllers in SystemVerilog. Provides functional platforms to the validation team for CPU to DDR functional verification and performance analysis.