44 English-speaking jobs in Cannes - Crasse

Principal Design Verification Engineer to design and deliver interconnect & memory hierarchy solutions for sophisticated SoCs. Responsibilities include UVM test bench development, RTL verification, and improving verification processes using scripting.

Post-Doctoral Research Visit on update-friendly data structures for 3D city modelling. Investigate generalizing line/plane arrangements and designing easily modifiable data structures for urban reconstruction. Requires Ph.D. in CS with expertise in 3D geometry.

Senior Verification Engineer to verify RTL for ARM SoC features. Requires 5+ years in IP/SOC verification, proficiency in SystemVerilog/UVM, and experience with ARM designs.

Lead SoC Interconnect Technology Team to drive architecture and design of coherent/non-coherent interconnect solutions. Requires 15+ years in SoC architecture with expertise in scalable fabrics, performance, and power optimization.