51 English-speaking jobs in Cannes - Crasse

Senior FPGA Prototyping Engineer to design and improve the FPGA prototyping workflow for complex CPU designs. Responsibilities include generating, testing, and debugging platforms from RTL using state-of-the-art FPGAs.

System Software Validation Engineer to ensure quality and reliability of software solutions. Design and execute test strategies, develop test cases, and verify firmware/software stacks. Requires 7+ years in software testing and strong technical knowledge.

Senior Emulation Engineer/Team Lead to drive emulation strategy and workflows for complex CPUs. Lead the team, define project tasks, and optimize platform deliveries using ASIC and emulation platform expertise.

Define, document, and drive system architecture for cutting-edge HPC systems. Lead architectural engagements with partners and customers to design optimized HPC nodes. Develop integration, performance measurement, and optimization tools. Contribute to collaborative projects, technical deliverables, and partner workshops. Support customers in migrating applications toward new system architectures.

Emulation Engineer role at SiPearl involves contributing to emulation setup, RTL adaptation, and pre-silicon verification. Key tasks include developing workflows, maintaining models, and supporting platform users. Requires 6+ years in digital ASIC and 4+ years on emulation platforms.

Experienced Project Engineer needed to manage complex Engineer-to-order projects in a marine environment. Own technical scope, lead discussions with shipyards and customers, and ensure successful project execution from handover to delivery.

Principal Design Verification Engineer to design and deliver interconnect & memory hierarchy solutions for sophisticated SoCs. Responsibilities include UVM test bench development, RTL verification, and improving verification processes using scripting.

Post-Doctoral Research Visit on update-friendly data structures for 3D city modelling. Investigate generalizing line/plane arrangements and designing easily modifiable data structures for urban reconstruction. Requires Ph.D. in CS with expertise in 3D geometry.

PhD position focused on spatio-temporal analysis of remote sensing data at large scales. The role involves developing methods for 3D change detection using geometric primitives and analyzing the distribution of these changes to understand urban evolution.

Senior Verification Engineer to verify RTL for ARM SoC features. Requires 5+ years in IP/SOC verification, proficiency in SystemVerilog/UVM, and experience with ARM designs.

Lead SoC Interconnect Technology Team to drive architecture and design of coherent/non-coherent interconnect solutions. Requires 15+ years in SoC architecture with expertise in scalable fabrics, performance, and power optimization.