93 English-speaking jobs in Cannes - Crasse

Voice Software Engineer to integrate and deploy real-time voice and audio algorithms for noise reduction, echo cancellation, and music playback in wearable devices.

Develop, maintain, and debug test programs for new product creation and production fulfillment. Support root-cause analysis for customer returns on ATE. Act as the technical owner for test programs and control changes using a structured process.

Develops and implements Low-Cost Carrier airline services worldwide. Manages services strategy, including profit and loss, portfolio, delivery, and sales support. Collaborates with internal partners and customers to ensure service delivery and business development.

Senior Principal SoC Physical Implementation/STA Engineer needed for end-to-end Physical implementation of Automotive and Industrial Automation Processors. Expertise in STA, timing constraints development, and timing closure required. Knowledge of synthesis, LEC, low power checks, and Physical Implementation (Place&Route) is a plus.

Senior Principal Vision and AI Engineer to lead architecture definition, technical exploration, and prototype development for vision and AI solutions on MPU/MCU platforms.

A postdoctoral position is available to evaluate the usability of "notice and action" reporting mechanisms on online platforms within the context of the EU Digital Services Act (DSA). The successful candidate will apply usability evaluation methods to assess the effectiveness and user-friendliness of these mechanisms.

Graduate engineer to improve CPU micro-architectural functionalities. Responsibilities include implementing improvements in a CPU performance model, analyzing performance gains, and verifying product performance. Requires a degree in Electronic Engineering or Computer Science, programming skills (preferably in C), and knowledge of CPU microarchitecture.

This 2-year postdoc position aims to develop a domain-agnostic algorithm for segmenting brain MRI scans across the human lifespan. The successful candidate will work with two leading research groups in medical image analysis, Inria and University College London. The project will extend domain randomisation to capture the unique characteristics of foetal and infant brains, integrating early-life and adult data into a single training framework.

Define, document, and drive system architecture for cutting-edge HPC systems. Lead architectural engagements with partners and customers to design optimized HPC nodes. Develop integration, performance measurement, and optimization tools. Contribute to collaborative projects, technical deliverables, and partner workshops.

As an AI Data Engineer, you will convert business problems into hypotheses, build, validate, and deploy models to solve them using methodologies, domain expertise, consulting, software engineering, statistics, and mathematics. You will collect and explore data, create models, and deploy them as code while ensuring their business value throughout their lifecycle.

Graduate engineer to join CPU verification team. Responsibilities include gathering requirements, understanding CPU micro-architecture, and developing solutions to improve test stimuli generation. Requires proficiency in programming and scripting languages, understanding of assembly language, and strong interpersonal skills.

Manages and develops ETSI's website, ensuring a consistent look and feel across all pages. Develops and maintains web editing guidelines, manages the editorial calendar, and reviews content. Creates digital assets (text, images, videos) aligned with the marketing communication plan. Tracks website performance and proposes improvements. Promotes ETSI activities online and manages social media support.

Momji seeks a part-time English nanny in CANNES for 4 hours per week to care for 1 child. Tasks include after-school and daycare pick-ups, homework help, snack time, hygiene assistance, and park visits. Previous experience with children is required. EU citizenship or a work visa is necessary.

Consulting Systems Engineer provides Public Cloud expertise to Sales, Sales Engineers, and Subject Matter Experts. Conducts PoVs, researches integrations with Fortinet's cybersecurity offerings, and supports key projects. Requires pre-sales experience, cloud platform knowledge (AWS, Azure, GCP), and strong presentation skills.

System Administrator Engineer to manage and optimize a technical infrastructure for Fortinet product validation. Responsibilities include Linux server and virtual machine administration, Docker container management, traffic generator administration, monitoring and alerting solutions management, application support, and ITIL process adherence.

Fortinet seeks Consulting Systems Engineers with deep networking and security knowledge to join the FortiGate/SASE Enterprise team. Responsibilities include providing design assistance, architectural advice, and product insight to sales staff. Candidates will conduct lab testing, deliver results through written documents and meetings, and provide technical assistance to sales teams. Strong networking skills, including IPv4/IPv6, routing protocols, VPNs, and security expertise are required. Excellent communication and presentation skills are also essential.

Intern will investigate architecture enhancements for the Scalable Matrix Extension (SME), supporting AI, Machine Learning, Computer Vision, telecommunication, and HPC applications. Responsibilities include analyzing applications and prototyping innovative instructions.

Senior Full-Stack Developer will design, develop, and deliver application modules for network security infrastructure. Requires 5+ years of experience in full-stack development, proficiency in JavaScript, HTML5, CSS3, Python, and Perl, and experience with RESTful APIs and web services.

Embedded Software Engineers develop next generation Wi-Fi technologies using low-level C for wireless communications and subsystems.

Designs and implements system level platforms for RTL simulation and FPGA emulation using Snapdragon IPs. Integrates CPUs, SMMU, interconnects, and memory controllers in SystemVerilog. Provides functional platforms to the validation team for CPU to DDR functional verification and performance analysis.