93 English-speaking jobs in Cannes - Crasse

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.

Network Security QA Engineer role involves post-sales testing to replicate customer environments. Requires strong network security experience, knowledge of TCP/IP, and proficiency with tools like Spirent/Ixia.

Designs, implements, and debugs FPGA-based functionality for mixed-signal systems using RTL development, simulation, and hardware validation. Supports development activities on Xilinx Zynq-based platforms, including logic integration, interface definition, and hardware/software interaction.

Support the Fleet Compliance Department to ensure managed vessels adhere to International, Flag, Class, and Local Regulations and the SMS. Duties include SMS review, regulatory management, and incident monitoring.

Develops industrial test solutions (hardware and software) for mass production of automotive radar products. Collaborates with design teams and drives deliverables to completion. Requires 10+ years of Analog, RF/mmW test development experience using ATE systems.

Leads innovation projects for Safe AI, translating the Safety & AI roadmap into projects. Defines system safety concepts for AI-driven features and ensures fail-safe or fail-operational behavior. Manages the “Safety & AI” innovation team.

Senior Satellite Systems Engineer provides resident systems engineering support across satellite procurement phases, including design, integration, and launch. Responsibilities involve reviewing test data and ensuring platform equipment meets performance requirements.

Senior Digital Design Engineer to join Bluetooth IP team. Responsible for macro/sub-system architecture, design, and verification of Bluetooth/15.4 MAC, PHY, and platform solutions. Requires 12+ years of digital design experience, 5+ years in architecture, and proficiency in Verilog/SystemVerilog. Must have a strong understanding of SoC and HW sub-systems architecture and the full design flow.

Oversee end-to-end implementation of Intellectual Property Management Systems. Requires 10+ years in software project management, strong communication, and technical understanding.

Seeking an experienced Executive Assistant & Office Manager to support the CEO and leadership team. Responsibilities include managing complex calendars, coordinating travel, and overseeing daily office operations. Requires 8+ years of executive support experience.

Consulting Systems Engineer relays Public Cloud expertise to sales teams, customers, and partners. Responsibilities include conducting PoVs, researching integrations, and supporting technical discussions for Fortinet's cybersecurity offerings.

FP&A Analyst role involving business reviews, group reporting, and budget/reforecast building. Requires 3+ years' experience, advanced accounting/Excel skills, and a rigorous, proactive approach.

Part-time Recruiter needed for a 5-month fixed-term contract. Responsibilities include pipeline assessment, candidate screening, and managing the applicant tracking system. Requires experience in talent acquisition, strong communication skills, and proficiency with ATS.

Verification Engineer needed to verify RISC-V processors and extensions. Develop verification solutions, collaborate with engineers, and define verification strategies. Requires experience with functional processor verification methodologies, CPU architectures, and languages like SystemVerilog, Python, C++, Rust, or Go.

Senior polyglot Software Engineer to design and build security integrations across libraries, focusing on .NET or Java. Own features from prototype to production, driving security value for thousands of applications.

Lead AI Safety definition and implementation for next-gen Automotive Compute Subsystems and SoCs for L4 autonomous driving and robotics. Develop safety architectures aligned with ISO 26262, SOTIF, and other standards.

Senior CAD flow engineer will define, deploy, and improve ASIC development methodology and design flow. Responsibilities include leading tool evaluation and optimization, providing technical support to development teams, and acting as a technical interface with vendors.

Senior IP subsystem SoC architect will define, drive, and evolve IP, subsystem, and SoC architectures. Responsibilities include breaking down architectures into functional sub-blocks, writing specifications, and supporting RTL, physical design, verification, and software prototyping teams.

SiPearl is seeking passionate individuals to contribute to the development of Rhea, a European microprocessor for supercomputing and AI.

Senior FPGA Prototyping Engineer to design and improve the FPGA prototyping workflow for complex CPU designs. Responsibilities include generating, testing, and debugging platforms from RTL using state-of-the-art FPGAs.