100 English-speaking jobs in Cannes - Crasse

Senior Verification Engineer to verify RTL for ARM SoC features. Requires 5+ years in IP/SOC verification, proficiency in SystemVerilog/UVM, and experience with ARM designs.

Oversee end-to-end implementation of Intellectual Property Management Systems. Requires 10+ years in software project management, strong communication, and technical understanding.

Senior Verification Engineer to verify RTL for ARM SoC features. Requires 3+ years in IP/SOC verification, proficiency in SystemVerilog/UVM, and experience with ARM designs.

FPGA Platform Lead for Secure Transactions & Interfaces (STI) team. Develops FPGA verification platforms, interfaces with design and software teams, defines FPGA strategy, and debugs designs. Requires 7+ years of experience in FPGA design flow, SoC architecture, and EDA tools.

Seeking an experienced Executive Assistant & Office Manager to support the CEO and leadership team. Responsibilities include managing complex calendars, coordinating travel, and overseeing daily office operations. Requires 8+ years of executive support experience.

Experienced Director of Product Marketing needed to drive market success for NFC IoT Security products. This role owns the full product lifecycle, from GTM strategy and positioning to market launch, collaborating with global teams. Requires 10+ years in semiconductor product marketing.

Oversee end-to-end IPMS implementation projects, ensuring delivery within scope, time, and budget. Requires 10+ years in project management, strong communication, and technical proficiency.

Experienced Project Engineer needed to manage complex Engineer-to-order projects in a marine environment. Own technical scope, lead discussions with shipyards and customers, and ensure successful project execution from handover to delivery.

Lead and develop the DFT team, ensuring successful project delivery and driving technical excellence in Design for Test methodologies.

Define, document, and drive system architecture for cutting-edge HPC systems. Lead architectural engagements with partners and customers to design optimized HPC nodes. Develop integration, performance measurement, and optimization tools. Contribute to collaborative projects, technical deliverables, and partner workshops. Support customers in migrating applications toward new system architectures.

Senior IP subsystem SoC architect will define, drive, and evolve IP, subsystem, and SoC architectures. Responsibilities include breaking down architectures into functional sub-blocks, writing specifications, and supporting RTL, physical design, verification, and software prototyping teams.

SiPearl is seeking passionate individuals to contribute to the development of Rhea, a European microprocessor for supercomputing and AI.

Emulation Engineer role at SiPearl involves contributing to emulation setup, RTL adaptation, and pre-silicon verification. Key tasks include developing workflows, maintaining models, and supporting platform users. Requires 6+ years in digital ASIC and 4+ years on emulation platforms.

Senior Emulation Engineer/Team Lead to drive emulation strategy and workflows for complex CPUs. Lead the team, define project tasks, and optimize platform deliveries using ASIC and emulation platform expertise.

System Software Validation Engineer to ensure quality and reliability of software solutions. Design and execute test strategies, develop test cases, and verify firmware/software stacks. Requires 7+ years in software testing and strong technical knowledge.

Senior CAD flow engineer will define, deploy, and improve ASIC development methodology and design flow. Responsibilities include leading tool evaluation and optimization, providing technical support to development teams, and acting as a technical interface with vendors.

Software Engineer to develop and optimize EDA software for eFPGA and ASIC design. Responsibilities include implementing GUI interfaces, working on synthesis, placement, routing, and STA algorithms, and collaborating with hardware and software engineers.

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.

Experienced Backend Engineer joins an agile scrum team to deliver user stories. Responsibilities include system design, coding in C++ or Java, database modeling, and software testing. Requires English proficiency.

EMEA Payroll Specialist manages regional payroll for 27 countries and 3500+ people. Responsibilities include processing complex items like RSUs, ensuring compliance, and managing third-party providers.