102 English-speaking jobs in Cannes - Crasse

Senior Verification Engineer to verify RTL for ARM SoC features. Requires 3+ years in IP/SOC verification, proficiency in SystemVerilog/UVM, and experience with ARM designs.

FPGA Platform Lead for Secure Transactions & Interfaces (STI) team. Develops FPGA verification platforms, interfaces with design and software teams, defines FPGA strategy, and debugs designs. Requires 7+ years of experience in FPGA design flow, SoC architecture, and EDA tools.

Principal Engineer to act as technical lead, solving complex challenges in Availability Computation. Responsibilities include designing, managing, and optimizing cloud infrastructure while ensuring high-quality, efficient code and driving engineering process improvements.

Principal Engineer to act as technical lead, solving complex challenges in Availability Computation. Requires deep software development experience, C++ knowledge, and driving technical excellence and process improvement.

Senior Technical Consultant Analyst supports customers using Revenue Management and Dynamic Pricing solutions. Responsibilities include customer communication, business acumen development, and applying data science to optimize commercial opportunities.

Senior Technical Consultant Analyst supports Revenue Management and Dynamic Pricing for airlines and mobility providers. Responsibilities include customer communication, business acumen, data science application, and business development. Requires a Master's degree and relevant industry experience.

Senior IP subsystem SoC architect will define, drive, and evolve IP, subsystem, and SoC architectures. Responsibilities include breaking down architectures into functional sub-blocks, writing specifications, and supporting RTL, physical design, verification, and software prototyping teams.

Define, document, and drive system architecture for cutting-edge HPC systems. Lead architectural engagements with partners and customers to design optimized HPC nodes. Develop integration, performance measurement, and optimization tools. Contribute to collaborative projects, technical deliverables, and partner workshops. Support customers in migrating applications toward new system architectures.

SiPearl is seeking passionate individuals to contribute to the development of Rhea, a European microprocessor for supercomputing and AI.

Emulation Engineer role at SiPearl involves contributing to emulation setup, RTL adaptation, and pre-silicon verification. Key tasks include developing workflows, maintaining models, and supporting platform users. Requires 6+ years in digital ASIC and 4+ years on emulation platforms.

Senior Emulation Engineer/Team Lead to drive emulation strategy and workflows for complex CPUs. Lead the team, define project tasks, and optimize platform deliveries using ASIC and emulation platform expertise.

Senior FPGA Prototyping Engineer to design and improve the FPGA prototyping workflow for complex CPU designs. Responsibilities include generating, testing, and debugging platforms from RTL using state-of-the-art FPGAs.

System Software Validation Engineer to ensure quality and reliability of software solutions. Design and execute test strategies, develop test cases, and verify firmware/software stacks. Requires 7+ years in software testing and strong technical knowledge.

Lead and develop the DFT team, ensuring successful project delivery and driving technical excellence in Design for Test methodologies.

Leads growth of the retrofit business by developing and executing go-to-market strategies and value propositions. Manages complex sales cycles, negotiates deals, and builds client relationships. Drives sustainable growth through pipeline development, customer engagement, and strategic account management.

Software Engineer to develop and optimize EDA software for eFPGA and ASIC design. Responsibilities include implementing GUI interfaces, working on synthesis, placement, routing, and STA algorithms, and collaborating with hardware and software engineers.

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.

Experienced Backend Engineer joins an agile scrum team to deliver user stories. Responsibilities include system design, coding in C++ or Java, database modeling, and software testing. Requires English proficiency.

EMEA Payroll Specialist manages regional payroll for 27 countries and 3500+ people. Responsibilities include processing complex items like RSUs, ensuring compliance, and managing third-party providers.

Senior Hardware AI Engineer to build AI-enabled automation improving hardware design and verification efficiency. Develop AI solutions using OpenAI Codex and integrate AI tools to transform engineering workflows.