88 English-speaking jobs in Cannes - Crasse

Seeking an experienced Executive Assistant & Office Manager to support the CEO and leadership team. Responsibilities include managing complex calendars, coordinating travel, and overseeing daily office operations. Requires 8+ years of executive support experience.

Oversee end-to-end IPMS implementation projects, ensuring delivery within scope, time, and budget. Requires 10+ years in project management, strong communication, and technical proficiency.

Senior FPGA Prototyping Engineer to design and improve the FPGA prototyping workflow for complex CPU designs. Responsibilities include generating, testing, and debugging platforms from RTL using state-of-the-art FPGAs.

Define, document, and drive system architecture for cutting-edge HPC systems. Lead architectural engagements with partners and customers to design optimized HPC nodes. Develop integration, performance measurement, and optimization tools. Contribute to collaborative projects, technical deliverables, and partner workshops. Support customers in migrating applications toward new system architectures.

SiPearl is seeking passionate individuals to contribute to the development of Rhea, a European microprocessor for supercomputing and AI.

Lead and develop the DFT team, ensuring successful project delivery and driving technical excellence in Design for Test methodologies.

Senior Emulation Engineer/Team Lead to drive emulation strategy and workflows for complex CPUs. Lead the team, define project tasks, and optimize platform deliveries using ASIC and emulation platform expertise.

Senior IP subsystem SoC architect will define, drive, and evolve IP, subsystem, and SoC architectures. Responsibilities include breaking down architectures into functional sub-blocks, writing specifications, and supporting RTL, physical design, verification, and software prototyping teams.

Emulation Engineer role at SiPearl involves contributing to emulation setup, RTL adaptation, and pre-silicon verification. Key tasks include developing workflows, maintaining models, and supporting platform users. Requires 6+ years in digital ASIC and 4+ years on emulation platforms.

Leads growth of the retrofit business by developing and executing go-to-market strategies and value propositions. Manages complex sales cycles, negotiates deals, and builds client relationships. Drives sustainable growth through pipeline development, customer engagement, and strategic account management.

Experienced Project Engineer needed to manage complex Engineer-to-order projects in a marine environment. Own technical scope, lead discussions with shipyards and customers, and ensure successful project execution from handover to delivery.

Manages Talent Development activities across campuses, translating strategic directions into action plans and ensuring program consistency.

Software Engineer to develop and optimize EDA software for eFPGA and ASIC design. Responsibilities include implementing GUI interfaces, working on synthesis, placement, routing, and STA algorithms, and collaborating with hardware and software engineers.

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.

Backend Engineer will design, develop, and maintain software solutions in an agile scrum team. Requires proficiency in C++ and/or Java, REST, JSON, XML, and EDIFACT. Experience with agile methodologies and English proficiency are essential.

The Recruitment Administrator supports the recruitment team by managing reception, screening applications, maintaining the database, and assisting with job postings and candidate support.

Senior Satellite Systems Engineer provides resident systems engineering support across satellite procurement phases, including design, integration, and launch. Responsibilities involve reviewing test data and ensuring platform equipment meets performance requirements.

Principal Design Verification Engineer to design and deliver interconnect & memory hierarchy solutions for sophisticated SoCs. Responsibilities include UVM test bench development, RTL verification, and improving verification processes using scripting and automation.

Observability Engineer to analyze, migrate, and design Dynatrace Synthetic Monitoring probes. Experience with Dynatrace Synthetic Monitoring and observability practices required.

Mechanic required for maintenance, repair, and delivery of motorized garden equipment. Must have experience with 2-stroke and 4-stroke engines and diagnostic tools. Minimum 3 years experience required.