110 English-speaking jobs in Cannes - Crasse

  • Hillcrest Labs, acquired by CEVA
  • valbonne
  • August 4
Digital Design Engineer to develop Bluetooth IP solutions. Define micro-architecture, implement designs, and support validation and customer support. Requires 3+ years of digital design experience, Verilog/SystemVerilog proficiency, and FPGA implementation skills.
  • Hillcrest Labs, acquired by CEVA
  • valbonne
  • August 4
Digital Design Engineer to join Bluetooth IP team developing state-of-the-art solutions. Define micro-architecture, implement designs, and support validation and customer support. Requires 3+ years of digital design and verification experience, strong Verilog/SystemVerilog skills, and FPGA implementation experience.
  • Fortinet
  • Valbonne
  • August 4
The Channel Operations Manager leads the EMEA Channel Operations team, ensuring consistent business processes and improving channel support activities. Responsibilities include managing workflows, tracking incentives, and analyzing channel requests. Requires 5+ years in channel/sales operations within cybersecurity or IT.
  • ARM
  • Valbonne
  • August 3
Lead security evaluations and certification programs for Arm products, coordinating with external labs. Ensure compliance with standards like Common Criteria, FIPS, and ISO 21434. Requires 10+ years in product security.
  • ARM
  • Valbonne
  • August 3
Staff Applications Engineer supports Arm's Physical AI platforms across Automotive and Robotics. This customer-facing role provides technical support, training, and documentation for partners on firmware and software issues. Requires 10+ years in firmware/software development with strong C/C++ skills.
  • Arteris
  • biot
  • August 3
Define and optimize cache coherency solutions within advanced IP portfolios. Develop cutting-edge cache coherent interconnect IP and ensure seamless integration with NoC and system IP.
  • NXP Semiconductors
  • valbonne
  • July 31
Shape next-gen NFC wallet, eSE, and eUICC solutions. Define product requirements, contribute to roadmaps, and bridge technical needs with customer value across mobile and IoT ecosystems.
  • Menta SAS
  • valbonne
  • July 28
Senior Hardware & Verification Engineer to lead and manage verification flows for complex hardware IP. Solid experience in RTL design and UVM-based verification required. Proficiency in Verilog/SystemVerilog/VHDL and EDA tools.
  • ALTEN
  • valbonne
  • July 28
Embedded Software Engineer will design, develop, and debug C/C++ software for embedded systems in real-time environments. Collaborate with multidisciplinary teams to integrate and validate software solutions.
  • Fortinet
  • Valbonne
  • July 28
Network Security QA Engineer role involves post-sales testing to replicate customer environments. Requires strong network security experience, knowledge of TCP/IP, and proficiency with tools like Spirent/Ixia.
  • Alten
  • Valbonne
  • July 28
DevOps Engineer to enhance development and deployment processes by automating workflows and ensuring system reliability. Responsibilities include optimizing infrastructure tools, automating tasks, and managing incidents. Requires a Master's degree and skills in Linux, Docker, Kubernetes, Bash, Python, and CI/CD tools.
  • Fortinet
  • Valbonne
  • July 28
Fortinet seeks an experienced Senior Full-Stack Developer to design and deliver application modules for network security infrastructure. Requires 5+ years in full-stack development, proficiency in React, Python, and node.js, and knowledge of cybersecurity.
  • ARM
  • Valbonne
  • July 28
This hybrid role requires hands-on technical ownership of building systems at the Sophia Antipolis site while standardizing maintenance practices across EMEA. Responsibilities include site operations, vendor management, and technical contribution to wider protocols.
  • NXP Semiconductors
  • valbonne
  • July 28
Leads the execution of solution development for the NXP CoreRide platform, ensuring alignment with customer needs and business objectives. Defines the solution vision, coordinates development progress across Agile Release Trains (ARTs) and suppliers, and supports the solution throughout its lifecycle.
  • Arteris
  • biot
  • July 28
Define and optimize cache coherency solutions for Arteris' NoC IP portfolio. Collaborate with hardware designers, verification engineers, and software developers to create high-performance, power-efficient, and reliable NoC IP solutions. Analyze customer requirements for cache-coherent system architectures and set performance goals for configurable IP.
  • NXP Semiconductors
  • Valbonne
  • July 28
Develop industrial test solutions (hardware and software) for mass production of Automotive Radar products. This role requires over 10 years of Analog, RF/mmW test development experience using ATE systems.
  • Fortinet, Inc.
  • valbonne
  • July 28
Internal Consulting Systems Engineer to support, evolve, and automate solutions and tools for the pre-sales department. This role requires cybersecurity expertise, systems engineering, and software development skills with a focus on automation, reliability, and secure-by-design solutions. Responsibilities include designing, building, and operating scalable platforms, troubleshooting security, network, and system issues, and developing and enhancing internal platforms, APIs, and automation.
  • NXP Semiconductors
  • valbonne
  • July 28
FPGA Platform Lead for Secure Transactions & Interfaces (STI) team. Develops FPGA verification platforms, interfaces with design and software teams, defines FPGA strategy, and debugs designs. Requires 7+ years of experience in FPGA design flow, SoC architecture, and EDA tools.
  • NXP Semiconductors
  • valbonne
  • July 28
Leads innovation projects for Safe AI, translating the Safety & AI roadmap into projects. Defines system safety concepts for AI-driven features and ensures fail-safe or fail-operational behavior. Manages the “Safety & AI” innovation team.
  • ARM
  • Valbonne
  • July 28
Analyze performance bottlenecks in Arm-based SoCs using simulation and hardware emulation. Investigate CPU, interconnect, memory, and I/O behavior under realistic workloads. Requires 5+ years experience and strong system architecture knowledge.
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