106 English-speaking jobs in Cannes - Crasse

Provides regulatory strategy and direction for AI software programs, supporting global registration planning, submissions, and post-market compliance. Develops regulatory strategies to optimize submission pathways, considering regulatory requirements, product claims, and country dependencies. Assesses changes to existing products and determines the need for new licenses or registrations.

Consulting Systems Engineer provides Public Cloud expertise to Sales, Sales Engineers, and Subject Matter Experts. Conducts PoVs, researches integrations with Fortinet's cybersecurity offerings, and supports key projects. Requires pre-sales experience, cloud platform knowledge (AWS, Azure, GCP), and strong presentation skills.

Software Engineer, Java Backend will design, implement, and deploy scalable Java-based microservices. Responsibilities include collaborating with product and engineering teams, investigating issues, and participating in code reviews. Requires an MSC in Computer Science and 3+ years of Java server-side development experience.

This internship focuses on formulating and analyzing mathematical models of plant-microbiota interactions. The candidate will analyze model dynamics, explore optimal control strategies for plant exudation, and compare theoretical models with different control implementations.

Momji is seeking an English-speaking nanny for a part-time position in ST LAURENT DU VAR. The role involves after-school and daycare pick-ups, homework assistance, snack time, hygiene support, and park outings. Previous experience with children is required.

As a Physical Implementation Engineer, you will be responsible for ASIC physical implementation of eFPGA IP architectures from RTL to GDSII. You will contribute to the development and maintenance of the internal design flow.

This role involves defining and implementing System & Performance validation plans for QCOM interconnects. Responsibilities include running test cases and Linux benchmarks on custom Emulators for latest CPU architectures. The engineer will also participate in infrastructure performance analysis and automation.

As a Cache Coherency Architect, you will define and optimize cache coherency solutions within Arteris' advanced IP portfolio. You will develop cache-coherent interconnect IP, ensuring seamless integration with other NoC interconnects and system IP. You will collaborate with hardware designers, verification engineers, software developers, and other stakeholders to create high-performance, power-efficient, and reliable NoC IP solutions.

IT Support Technician (Level 1 & 2) will provide technical maintenance of IT equipment, troubleshoot hardware and software issues, and contribute to IT service improvement.

System Administrator Engineer to manage and optimize a technical infrastructure for Fortinet product validation. Responsibilities include Linux server and virtual machine administration, Docker container management, traffic generator administration, monitoring and alerting solutions management, application support, and ITIL process adherence.

Define and study micro-architectural improvements for next-generation CPUs. Implement performance features in a micro-architectural performance model and analyze performance data. Contribute to performance analysis methodology improvements.

Designs and scales evaluation systems to measure the performance and reliability of AI models. Builds human-in-the-loop and automated annotation pipelines for model assessment. Defines and implements continuous evaluation workflows to monitor model behavior. Collaborates cross-functionally to establish best practices for responsible AI.

Designs and implements system level platforms for RTL simulation and FPGA emulation using Snapdragon IPs. Integrates CPUs, SMMU, interconnects, and memory controllers in SystemVerilog. Provides functional platforms to the validation team for CPU to DDR functional verification and performance analysis.

STA expert engineer to develop next-generation ASICs. Responsibilities include timing constraint generation, tool settings for sign-off, and top-level STA. Requires 5+ years of experience in timing constraints and convergence, expertise in Synopsys or Cadence STA tools, and knowledge of ASIC design flow.

Mechanical & CFD Engineer to contribute to product development, including design, simulation, and testing. Requires a Master's/PhD in engineering with experience in CAD, material science, and CFD. Fluency in English is required.

Designs and implements system level platforms for RTL simulation and FPGA emulation using Snapdragon IPs. Integrates CPUs, SMMU, interconnects, and memory controllers in SystemVerilog. Provides functional platforms to the validation team for CPU to DDR functional verification and performance analysis.

Experienced live-in couple sought for private villa in Antibes. Responsibilities include driving, property maintenance, house cleaning, and wardrobe care. Must have similar experience and no bad habits.

Composite Design Engineer will plan, manage, and liaise on engineering projects. The role involves conceptual and detailed design, analysis, and development of composite engineering solutions. Requires a Bachelor's or Master's Degree in Engineering, Material Science, or related field and experience with structural composite materials. Fluent English required.

Software Engineer to develop next-generation Wi-Fi connectivity solutions for CEVA's IP platforms. Focus on low-level C development, firmware design, and system-level architecture. Requires 5+ years of embedded software development experience, proficiency in C/C++, Linux, and embedded OSes, and strong technical background in Wi-Fi protocols (802.11 standards), MAC/PHY layers, and system-level software design.

Digital logic designer for SuperComputer applications. Designs digital circuits (FPGA or ASIC) with focus on area and power efficiency. Requires 5+ years experience in digital logic design and strong knowledge of VHDL or Verilog.